EE 565 - Parallel and Associative Processors

Class Web site .

Project

One of our biggest tasks for the semester was to choose a project to implement in a Xilinx FPGA. The project could be implemented on parallel soft microprocessors or as a data flow architecture. I decided to implement as much as I could of a hardware JPEG image compressor.

Here is my project proposal. (It's in Microsoft Word format - here's an HTML version).

Here is my final report on the project. (Also in Microsoft Word format.)

And here is the presentation I gave. (In Microsoft PowerPoint format.)

Here are a number of the files that I produced as part of the project:

Source code for Microblaze	project.c
.MPD file for JPEG device	opb_jpeg_v2_0_0.mpd
.PAO file for JPEG device	opb_jpeg_v2_0_0.pao
Top-level VHDL for JPEG device	opb_jpeg.vhd
Implementation VHDL (a stub, actually) for JPEG device core	jpeg_core.vhd