\section{include/sys/h8.h File Reference}
\label{h8_8h}\index{include/sys/h8.h@{include/sys/h8.h}}
Internal Interface: H8/3297 processor registers. 

\subsection*{Defines}
\begin{CompactItemize}
\item 
\#define {\bf TIER\_\-ENABLE\_\-ICA}\ 0x80
\item 
\#define {\bf TIER\_\-ENABLE\_\-ICB}\ 0x40
\item 
\#define {\bf TIER\_\-ENABLE\_\-ICC}\ 0x20
\item 
\#define {\bf TIER\_\-ENABLE\_\-ICD}\ 0x10
\item 
\#define {\bf TIER\_\-ENABLE\_\-OCA}\ 0x08
\item 
\#define {\bf TIER\_\-ENABLE\_\-OCB}\ 0x04
\item 
\#define {\bf TIER\_\-ENABLE\_\-OF}\ 0x02
\item 
\#define {\bf TIER\_\-RESERVED}\ 0x01
\item 
\#define {\bf TCSR\_\-ICA}\ 0x80
\item 
\#define {\bf TCSR\_\-ICB}\ 0x40
\item 
\#define {\bf TCSR\_\-ICC}\ 0x20
\item 
\#define {\bf TCSR\_\-ICD}\ 0x10
\item 
\#define {\bf TCSR\_\-OCA}\ 0x08
\item 
\#define {\bf TCSR\_\-OCB}\ 0x04
\item 
\#define {\bf TCSR\_\-OF}\ 0x02
\item 
\#define {\bf TCSR\_\-RESET\_\-ON\_\-A}\ 0x01
\item 
\#define {\bf TCR\_\-A\_\-RISING}\ 0x80
\item 
\#define {\bf TCR\_\-B\_\-RISING}\ 0x40
\item 
\#define {\bf TCR\_\-C\_\-RISING}\ 0x20
\item 
\#define {\bf TCR\_\-D\_\-RISING}\ 0x10
\item 
\#define {\bf TCR\_\-BUFFER\_\-A}\ 0x08
\item 
\#define {\bf TCR\_\-BUFFER\_\-B}\ 0x04
\item 
\#define {\bf TCR\_\-CLOCK\_\-2}\ 0x00
\item 
\#define {\bf TCR\_\-CLOCK\_\-8}\ 0x01
\item 
\#define {\bf TCR\_\-CLOCK\_\-32}\ 0x02
\item 
\#define {\bf TCR\_\-CLOCK\_\-EXT}\ 0x03
\item 
\#define {\bf TOCR\_\-OCRA}\ 0x00
\item 
\#define {\bf TOCR\_\-OCRB}\ 0x10
\item 
\#define {\bf TOCR\_\-ENABLE\_\-A}\ 0x08
\item 
\#define {\bf TOCR\_\-ENABLE\_\-B}\ 0x04
\item 
\#define {\bf TOCR\_\-HIGH\_\-LEVEL\_\-A}\ 0x02
\item 
\#define {\bf TOCR\_\-HIGH\_\-LEVEL\_\-B}\ 0x01
\item 
\#define {\bf CR\_\-ENABLE\_\-IRQA}\ 0x40
\item 
\#define {\bf CR\_\-ENABLE\_\-IRQB}\ 0x80
\item 
\#define {\bf CR\_\-ENABLE\_\-IRQO}\ 0x20
\item 
\#define {\bf CR\_\-CLEAR\_\-NEVER}\ 0x00
\item 
\#define {\bf CR\_\-CLEAR\_\-ON\_\-A}\ 0x08
\item 
\#define {\bf CR\_\-CLEAR\_\-ON\_\-B}\ 0x10
\item 
\#define {\bf CR\_\-CLEAR\_\-ON\_\-EXTERN}\ 0x18
\item 
\#define {\bf CSR\_\-MATCH\_\-A}\ 0x40
\item 
\#define {\bf CSR\_\-MATCH\_\-B}\ 0x80
\item 
\#define {\bf CSR\_\-OVERFLOW}\ 0x20
\item 
\#define {\bf CSR\_\-IGNORE\_\-B}\ 0x00
\item 
\#define {\bf CSR\_\-0\_\-ON\_\-B}\ 0x04
\item 
\#define {\bf CSR\_\-1\_\-ON\_\-B}\ 0x08
\item 
\#define {\bf CSR\_\-TOGGLE\_\-ON\_\-B}\ 0x0c
\item 
\#define {\bf CSR\_\-IGNORE\_\-A}\ 0x00
\item 
\#define {\bf CSR\_\-0\_\-ON\_\-A}\ 0x01
\item 
\#define {\bf CSR\_\-1\_\-ON\_\-A}\ 0x02
\item 
\#define {\bf CSR\_\-TOGGLE\_\-ON\_\-A}\ 0x03
\item 
\#define {\bf SMR\_\-SYNC}\ 0x80
\item 
\#define {\bf SMR\_\-ASYNC}\ 0x00
\item 
\#define {\bf SMR\_\-7BIT}\ 0x40
\item 
\#define {\bf SMR\_\-8BIT}\ 0x00
\item 
\#define {\bf SMR\_\-P\_\-NONE}\ 0x00
\item 
\#define {\bf SMR\_\-P\_\-EVEN}\ 0x20
\item 
\#define {\bf SMR\_\-P\_\-ODD}\ 0x30
\item 
\#define {\bf SMR\_\-1STOP}\ 0x00
\item 
\#define {\bf SMR\_\-2STOP}\ 0x08
\item 
\#define {\bf SMR\_\-MP}\ 0x04
\item 
\#define {\bf SMR\_\-CLOCK}\ 0x00
\item 
\#define {\bf SMR\_\-CLOCK\_\-4}\ 0x01
\item 
\#define {\bf SMR\_\-CLOCK\_\-16}\ 0x02
\item 
\#define {\bf SMR\_\-CLOCK\_\-64}\ 0x03
\item 
\#define {\bf SCR\_\-TX\_\-IRQ}\ 0x80
\item 
\#define {\bf SCR\_\-RX\_\-IRQ}\ 0x40
\item 
\#define {\bf SCR\_\-TRANSMIT}\ 0x20
\item 
\#define {\bf SCR\_\-RECEIVE}\ 0x10
\item 
\#define {\bf SCR\_\-MP\_\-IRQ}\ 0x08
\item 
\#define {\bf SCR\_\-TE\_\-IRQ}\ 0x04
\item 
\#define {\bf SCR\_\-INT\_\-CLOCK}\ 0x00
\item 
\#define {\bf SCR\_\-EXT\_\-CLOCK}\ 0x02
\item 
\#define {\bf SCR\_\-CLOCK\_\-OUT}\ 0x01
\item 
\#define {\bf SSR\_\-TRANS\_\-EMPTY}\ 0x80
\item 
\#define {\bf SSR\_\-RECV\_\-FULL}\ 0x40
\item 
\#define {\bf SSR\_\-OVERRUN\_\-ERR}\ 0x20
\item 
\#define {\bf SSR\_\-FRAMING\_\-ERR}\ 0x10
\item 
\#define {\bf SSR\_\-PARITY\_\-ERR}\ 0x08
\item 
\#define {\bf SSR\_\-ERRORS}\ 0x38
\item 
\#define {\bf SSR\_\-TRANS\_\-END}\ 0x04
\item 
\#define {\bf SSR\_\-MP}\ 0x02
\item 
\#define {\bf SSR\_\-MP\_\-TRANSFER}\ 0x01
\item 
\#define {\bf B2400}\ 207
\item 
\#define {\bf B4800}\ 103
\item 
\#define {\bf B9600}\ 51
\item 
\#define {\bf B19200}\ 25
\item 
\#define {\bf B38400}\ 12
\item 
\#define {\bf ADCSR\_\-END}\ 0x80
\item 
\#define {\bf ADCSR\_\-ENABLE\_\-IRQ}\ 0x40
\item 
\#define {\bf ADCSR\_\-START}\ 0x20
\item 
\#define {\bf ADCSR\_\-SCAN}\ 0x10
\item 
\#define {\bf ADCSR\_\-TIME\_\-266}\ 0x00
\item 
\#define {\bf ADCSR\_\-TIME\_\-134}\ 0x08
\item 
\#define {\bf ADCSR\_\-GROUP\_\-0}\ 0x00
\item 
\#define {\bf ADCSR\_\-GROUP\_\-1}\ 0x04
\item 
\#define {\bf ADCSR\_\-AN\_\-0}\ 0x00
\item 
\#define {\bf ADCSR\_\-AN\_\-1}\ 0x01
\item 
\#define {\bf ADCSR\_\-AN\_\-2}\ 0x02
\item 
\#define {\bf ADCSR\_\-AN\_\-3}\ 0x03
\item 
\#define {\bf ADCR\_\-EXTERN}\ 0x80
\item 
\#define {\bf SYSCR\_\-SOFTWARE\_\-STANDBY}\ 0x80
\item 
\#define {\bf WDT\_\-CSR\_\-PASSWORD}\ (0x\-A500)
\item 
\#define {\bf WDT\_\-CSR\_\-ENABLE}\ (0x0020)
\item 
\#define {\bf WDT\_\-CSR\_\-MODE\_\-WATCHDOG}\ (0x0040)
\item 
\#define {\bf WDT\_\-CSR\_\-MODE\_\-OVERFLOW}\ (0x0000)
\item 
\#define {\bf WDT\_\-CSR\_\-WATCHDOG\_\-NMI}\ (0x0000)
\item 
\#define {\bf WDT\_\-CSR\_\-WATCHDOG\_\-RES}\ (0x0008)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-2}\ (0x0000)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-32}\ (0x0001)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-64}\ (0x0002)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-128}\ (0x0003)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-256}\ (0x0004)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-512}\ (0x0005)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-2048}\ (0x0006)
\item 
\#define {\bf WDT\_\-CSR\_\-CLOCK\_\-4096}\ (0x0007)
\item 
\#define {\bf WDT\_\-CNT\_\-PASSWORD}\ (0x5A00)
\item 
\#define {\bf WDT\_\-CNT\_\-CLEAR}\ (0x0000)
\item 
\#define {\bf WDT\_\-CNT\_\-MSEC\_\-64}\ (0x0006)
\end{CompactItemize}
\subsection*{Variables}
\begin{CompactItemize}
\item 
unsigned char {\bf T\_\-IER}
\begin{CompactList}\small\item\em 16-bit timer interrupt enable register \item\end{CompactList}\item 
volatile unsigned char {\bf T\_\-CSR}
\begin{CompactList}\small\item\em 16-bit timer control / status register \item\end{CompactList}\item 
volatile unsigned {\bf T\_\-CNT}
\begin{CompactList}\small\item\em 16-bit timer count register \item\end{CompactList}\item 
unsigned {\bf T\_\-OCRA}
\begin{CompactList}\small\item\em 16-bit timer output compare register A \item\end{CompactList}\item 
unsigned {\bf T\_\-OCRB}
\begin{CompactList}\small\item\em 16-bit timer output compare register B \item\end{CompactList}\item 
unsigned char {\bf T\_\-CR}
\begin{CompactList}\small\item\em 16-bit timer control register \item\end{CompactList}\item 
unsigned char {\bf T\_\-OCR}
\begin{CompactList}\small\item\em 16-bit timer output control register \item\end{CompactList}\item 
volatile unsigned {\bf T\_\-ICRA}
\begin{CompactList}\small\item\em 16-bit timer input capture A register \item\end{CompactList}\item 
volatile unsigned {\bf T\_\-ICRB}
\begin{CompactList}\small\item\em 16-bit timer input capture B register \item\end{CompactList}\item 
volatile unsigned {\bf T\_\-ICRC}
\begin{CompactList}\small\item\em 16-bit timer input capture C register \item\end{CompactList}\item 
volatile unsigned {\bf T\_\-ICRD}
\begin{CompactList}\small\item\em 16-bit timer input capture D register \item\end{CompactList}\item 
unsigned char {\bf STCR}
\begin{CompactList}\small\item\em serial / timer control register \item\end{CompactList}\item 
unsigned char {\bf T0\_\-CR}
\begin{CompactList}\small\item\em timer 0 control register \item\end{CompactList}\item 
volatile unsigned char {\bf T0\_\-CSR}
\begin{CompactList}\small\item\em timer 0 control / status register \item\end{CompactList}\item 
unsigned char {\bf T0\_\-CORA}
\begin{CompactList}\small\item\em timer 0 constant A register \item\end{CompactList}\item 
unsigned char {\bf T0\_\-CORB}
\begin{CompactList}\small\item\em timer 0 constant B register \item\end{CompactList}\item 
volatile unsigned char {\bf T0\_\-CNT}
\begin{CompactList}\small\item\em timer 0 counter register \item\end{CompactList}\item 
unsigned char {\bf T1\_\-CR}
\begin{CompactList}\small\item\em timer 1 control register \item\end{CompactList}\item 
volatile unsigned char {\bf T1\_\-CSR}
\begin{CompactList}\small\item\em timer 1 control / status register \item\end{CompactList}\item 
unsigned char {\bf T1\_\-CORA}
\begin{CompactList}\small\item\em timer 1 constant A register \item\end{CompactList}\item 
unsigned char {\bf T1\_\-CORB}
\begin{CompactList}\small\item\em timer 1 constant B register \item\end{CompactList}\item 
volatile unsigned char {\bf T1\_\-CNT}
\begin{CompactList}\small\item\em timer 1 counter register \item\end{CompactList}\item 
volatile unsigned char {\bf S\_\-RDR}
\begin{CompactList}\small\item\em serial receive data register \item\end{CompactList}\item 
unsigned char {\bf S\_\-TDR}
\begin{CompactList}\small\item\em serial transmit data register \item\end{CompactList}\item 
unsigned char {\bf S\_\-MR}
\begin{CompactList}\small\item\em serial mode register \item\end{CompactList}\item 
unsigned char {\bf S\_\-CR}
\begin{CompactList}\small\item\em serial control register \item\end{CompactList}\item 
volatile unsigned char {\bf S\_\-SR}
\begin{CompactList}\small\item\em serial status register \item\end{CompactList}\item 
unsigned char {\bf S\_\-BRR}
\begin{CompactList}\small\item\em serial baud rate register \item\end{CompactList}\item 
unsigned char {\bf S\_\-TCR}
\begin{CompactList}\small\item\em serial / timer control register \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-A\_\-H}
\begin{CompactList}\small\item\em A/D converter data register A high. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-A\_\-L}
\begin{CompactList}\small\item\em A/D converter data register A low. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-B\_\-H}
\begin{CompactList}\small\item\em A/D converter data register B high. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-B\_\-L}
\begin{CompactList}\small\item\em A/D converter data register B low. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-C\_\-H}
\begin{CompactList}\small\item\em A/D converter data register C high. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-C\_\-L}
\begin{CompactList}\small\item\em A/D converter data register C low. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-D\_\-H}
\begin{CompactList}\small\item\em A/D converter data register D high. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-D\_\-L}
\begin{CompactList}\small\item\em A/D converter data register D low. \item\end{CompactList}\item 
volatile unsigned {\bf AD\_\-A}
\begin{CompactList}\small\item\em A/D converter data register A. \item\end{CompactList}\item 
volatile unsigned {\bf AD\_\-B}
\begin{CompactList}\small\item\em A/D converter data register B. \item\end{CompactList}\item 
volatile unsigned {\bf AD\_\-C}
\begin{CompactList}\small\item\em A/D converter data register C. \item\end{CompactList}\item 
volatile unsigned {\bf AD\_\-D}
\begin{CompactList}\small\item\em A/D converter data register D. \item\end{CompactList}\item 
volatile unsigned char {\bf AD\_\-CSR}
\begin{CompactList}\small\item\em A/D converter control / status register. \item\end{CompactList}\item 
unsigned char {\bf AD\_\-CR}
\begin{CompactList}\small\item\em A/D converter control register. \item\end{CompactList}\item 
unsigned char {\bf SYSCR}
\begin{CompactList}\small\item\em system control register \item\end{CompactList}\item 
unsigned char {\bf PORT1\_\-PCR}
\begin{CompactList}\small\item\em port 1 input pull-up control register \item\end{CompactList}\item 
unsigned char {\bf PORT2\_\-PCR}
\begin{CompactList}\small\item\em port 2 input pull-up control register \item\end{CompactList}\item 
unsigned char {\bf PORT3\_\-PCR}
\begin{CompactList}\small\item\em port 3 input pull-up control register \item\end{CompactList}\item 
unsigned char {\bf PORT1\_\-DDR}
\begin{CompactList}\small\item\em port 1 data direction register \item\end{CompactList}\item 
volatile unsigned char {\bf PORT1}
\begin{CompactList}\small\item\em port 1 I/O register \item\end{CompactList}\item 
unsigned char {\bf PORT2\_\-DDR}
\begin{CompactList}\small\item\em port 2 data direction register \item\end{CompactList}\item 
volatile unsigned char {\bf PORT2}
\begin{CompactList}\small\item\em port 2 I/O register \item\end{CompactList}\item 
unsigned char {\bf PORT3\_\-DDR}
\begin{CompactList}\small\item\em port 3 data direction register \item\end{CompactList}\item 
volatile unsigned char {\bf PORT3}
\begin{CompactList}\small\item\em port 3 I/O register \item\end{CompactList}\item 
unsigned char {\bf PORT4\_\-DDR}
\begin{CompactList}\small\item\em port 4 data direction register \item\end{CompactList}\item 
volatile unsigned char {\bf PORT4}
\begin{CompactList}\small\item\em port 4 I/O register \item\end{CompactList}\item 
unsigned char {\bf PORT5\_\-DDR}
\begin{CompactList}\small\item\em port 5 data direction register \item\end{CompactList}\item 
volatile unsigned char {\bf PORT5}
\begin{CompactList}\small\item\em port 5 I/O register \item\end{CompactList}\item 
unsigned char {\bf PORT6\_\-DDR}
\begin{CompactList}\small\item\em port 6 data direction register \item\end{CompactList}\item 
volatile unsigned char {\bf PORT6}
\begin{CompactList}\small\item\em port 6 I/O register \item\end{CompactList}\item 
volatile unsigned char {\bf PORT7}
\begin{CompactList}\small\item\em port 7 input register \item\end{CompactList}\item 
volatile unsigned int {\bf WDT\_\-CSR}
\begin{CompactList}\small\item\em watch dog timer control register \item\end{CompactList}\item 
volatile unsigned char {\bf WDT\_\-CNT}
\begin{CompactList}\small\item\em watch dog timer counter register \item\end{CompactList}\end{CompactItemize}


\subsection{Detailed Description}
Internal Interface: H8/3297 processor registers. 

\begin{Desc}
\item[Author:]Markus L. Noga $<${\tt markus@noga.de}$>$\end{Desc}


Definition in file {\bf h8.h}.

\subsection{Define Documentation}
\index{h8.h@{h8.h}!ADCR_EXTERN@{ADCR\_\-EXTERN}}
\index{ADCR_EXTERN@{ADCR\_\-EXTERN}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCR\_\-EXTERN\ 0x80}\label{h8_8h_a99}




Definition at line 351 of file h8.h.\index{h8.h@{h8.h}!ADCSR_AN_0@{ADCSR\_\-AN\_\-0}}
\index{ADCSR_AN_0@{ADCSR\_\-AN\_\-0}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-AN\_\-0\ 0x00}\label{h8_8h_a95}




Definition at line 342 of file h8.h.\index{h8.h@{h8.h}!ADCSR_AN_1@{ADCSR\_\-AN\_\-1}}
\index{ADCSR_AN_1@{ADCSR\_\-AN\_\-1}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-AN\_\-1\ 0x01}\label{h8_8h_a96}




Definition at line 343 of file h8.h.\index{h8.h@{h8.h}!ADCSR_AN_2@{ADCSR\_\-AN\_\-2}}
\index{ADCSR_AN_2@{ADCSR\_\-AN\_\-2}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-AN\_\-2\ 0x02}\label{h8_8h_a97}




Definition at line 344 of file h8.h.\index{h8.h@{h8.h}!ADCSR_AN_3@{ADCSR\_\-AN\_\-3}}
\index{ADCSR_AN_3@{ADCSR\_\-AN\_\-3}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-AN\_\-3\ 0x03}\label{h8_8h_a98}




Definition at line 345 of file h8.h.\index{h8.h@{h8.h}!ADCSR_ENABLE_IRQ@{ADCSR\_\-ENABLE\_\-IRQ}}
\index{ADCSR_ENABLE_IRQ@{ADCSR\_\-ENABLE\_\-IRQ}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-ENABLE\_\-IRQ\ 0x40}\label{h8_8h_a88}




Definition at line 333 of file h8.h.\index{h8.h@{h8.h}!ADCSR_END@{ADCSR\_\-END}}
\index{ADCSR_END@{ADCSR\_\-END}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-END\ 0x80}\label{h8_8h_a87}




Definition at line 332 of file h8.h.\index{h8.h@{h8.h}!ADCSR_GROUP_0@{ADCSR\_\-GROUP\_\-0}}
\index{ADCSR_GROUP_0@{ADCSR\_\-GROUP\_\-0}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-GROUP\_\-0\ 0x00}\label{h8_8h_a93}




Definition at line 339 of file h8.h.\index{h8.h@{h8.h}!ADCSR_GROUP_1@{ADCSR\_\-GROUP\_\-1}}
\index{ADCSR_GROUP_1@{ADCSR\_\-GROUP\_\-1}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-GROUP\_\-1\ 0x04}\label{h8_8h_a94}




Definition at line 340 of file h8.h.\index{h8.h@{h8.h}!ADCSR_SCAN@{ADCSR\_\-SCAN}}
\index{ADCSR_SCAN@{ADCSR\_\-SCAN}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-SCAN\ 0x10}\label{h8_8h_a90}




Definition at line 335 of file h8.h.\index{h8.h@{h8.h}!ADCSR_START@{ADCSR\_\-START}}
\index{ADCSR_START@{ADCSR\_\-START}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-START\ 0x20}\label{h8_8h_a89}




Definition at line 334 of file h8.h.\index{h8.h@{h8.h}!ADCSR_TIME_134@{ADCSR\_\-TIME\_\-134}}
\index{ADCSR_TIME_134@{ADCSR\_\-TIME\_\-134}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-TIME\_\-134\ 0x08}\label{h8_8h_a92}




Definition at line 337 of file h8.h.\index{h8.h@{h8.h}!ADCSR_TIME_266@{ADCSR\_\-TIME\_\-266}}
\index{ADCSR_TIME_266@{ADCSR\_\-TIME\_\-266}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define ADCSR\_\-TIME\_\-266\ 0x00}\label{h8_8h_a91}




Definition at line 336 of file h8.h.\index{h8.h@{h8.h}!B19200@{B19200}}
\index{B19200@{B19200}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define B19200\ 25}\label{h8_8h_a85}




Definition at line 268 of file h8.h.\index{h8.h@{h8.h}!B2400@{B2400}}
\index{B2400@{B2400}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define B2400\ 207}\label{h8_8h_a82}




Definition at line 265 of file h8.h.

Referenced by rcx\_\-init(), and rcx\-Init().\index{h8.h@{h8.h}!B38400@{B38400}}
\index{B38400@{B38400}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define B38400\ 12}\label{h8_8h_a86}




Definition at line 269 of file h8.h.\index{h8.h@{h8.h}!B4800@{B4800}}
\index{B4800@{B4800}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define B4800\ 103}\label{h8_8h_a83}




Definition at line 266 of file h8.h.

Referenced by rcx\_\-init(), and rcx\-Init().\index{h8.h@{h8.h}!B9600@{B9600}}
\index{B9600@{B9600}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define B9600\ 51}\label{h8_8h_a84}




Definition at line 267 of file h8.h.\index{h8.h@{h8.h}!CR_CLEAR_NEVER@{CR\_\-CLEAR\_\-NEVER}}
\index{CR_CLEAR_NEVER@{CR\_\-CLEAR\_\-NEVER}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CR\_\-CLEAR\_\-NEVER\ 0x00}\label{h8_8h_a35}




Definition at line 166 of file h8.h.\index{h8.h@{h8.h}!CR_CLEAR_ON_A@{CR\_\-CLEAR\_\-ON\_\-A}}
\index{CR_CLEAR_ON_A@{CR\_\-CLEAR\_\-ON\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CR\_\-CLEAR\_\-ON\_\-A\ 0x08}\label{h8_8h_a36}




Definition at line 167 of file h8.h.\index{h8.h@{h8.h}!CR_CLEAR_ON_B@{CR\_\-CLEAR\_\-ON\_\-B}}
\index{CR_CLEAR_ON_B@{CR\_\-CLEAR\_\-ON\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CR\_\-CLEAR\_\-ON\_\-B\ 0x10}\label{h8_8h_a37}




Definition at line 168 of file h8.h.\index{h8.h@{h8.h}!CR_CLEAR_ON_EXTERN@{CR\_\-CLEAR\_\-ON\_\-EXTERN}}
\index{CR_CLEAR_ON_EXTERN@{CR\_\-CLEAR\_\-ON\_\-EXTERN}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CR\_\-CLEAR\_\-ON\_\-EXTERN\ 0x18}\label{h8_8h_a38}




Definition at line 169 of file h8.h.\index{h8.h@{h8.h}!CR_ENABLE_IRQA@{CR\_\-ENABLE\_\-IRQA}}
\index{CR_ENABLE_IRQA@{CR\_\-ENABLE\_\-IRQA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CR\_\-ENABLE\_\-IRQA\ 0x40}\label{h8_8h_a32}




Definition at line 162 of file h8.h.\index{h8.h@{h8.h}!CR_ENABLE_IRQB@{CR\_\-ENABLE\_\-IRQB}}
\index{CR_ENABLE_IRQB@{CR\_\-ENABLE\_\-IRQB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CR\_\-ENABLE\_\-IRQB\ 0x80}\label{h8_8h_a33}




Definition at line 163 of file h8.h.\index{h8.h@{h8.h}!CR_ENABLE_IRQO@{CR\_\-ENABLE\_\-IRQO}}
\index{CR_ENABLE_IRQO@{CR\_\-ENABLE\_\-IRQO}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CR\_\-ENABLE\_\-IRQO\ 0x20}\label{h8_8h_a34}




Definition at line 164 of file h8.h.\index{h8.h@{h8.h}!CSR_0_ON_A@{CSR\_\-0\_\-ON\_\-A}}
\index{CSR_0_ON_A@{CSR\_\-0\_\-ON\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-0\_\-ON\_\-A\ 0x01}\label{h8_8h_a47}




Definition at line 188 of file h8.h.\index{h8.h@{h8.h}!CSR_0_ON_B@{CSR\_\-0\_\-ON\_\-B}}
\index{CSR_0_ON_B@{CSR\_\-0\_\-ON\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-0\_\-ON\_\-B\ 0x04}\label{h8_8h_a43}




Definition at line 183 of file h8.h.\index{h8.h@{h8.h}!CSR_1_ON_A@{CSR\_\-1\_\-ON\_\-A}}
\index{CSR_1_ON_A@{CSR\_\-1\_\-ON\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-1\_\-ON\_\-A\ 0x02}\label{h8_8h_a48}




Definition at line 189 of file h8.h.\index{h8.h@{h8.h}!CSR_1_ON_B@{CSR\_\-1\_\-ON\_\-B}}
\index{CSR_1_ON_B@{CSR\_\-1\_\-ON\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-1\_\-ON\_\-B\ 0x08}\label{h8_8h_a44}




Definition at line 184 of file h8.h.\index{h8.h@{h8.h}!CSR_IGNORE_A@{CSR\_\-IGNORE\_\-A}}
\index{CSR_IGNORE_A@{CSR\_\-IGNORE\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-IGNORE\_\-A\ 0x00}\label{h8_8h_a46}




Definition at line 187 of file h8.h.\index{h8.h@{h8.h}!CSR_IGNORE_B@{CSR\_\-IGNORE\_\-B}}
\index{CSR_IGNORE_B@{CSR\_\-IGNORE\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-IGNORE\_\-B\ 0x00}\label{h8_8h_a42}




Definition at line 182 of file h8.h.\index{h8.h@{h8.h}!CSR_MATCH_A@{CSR\_\-MATCH\_\-A}}
\index{CSR_MATCH_A@{CSR\_\-MATCH\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-MATCH\_\-A\ 0x40}\label{h8_8h_a39}




Definition at line 178 of file h8.h.\index{h8.h@{h8.h}!CSR_MATCH_B@{CSR\_\-MATCH\_\-B}}
\index{CSR_MATCH_B@{CSR\_\-MATCH\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-MATCH\_\-B\ 0x80}\label{h8_8h_a40}




Definition at line 179 of file h8.h.\index{h8.h@{h8.h}!CSR_OVERFLOW@{CSR\_\-OVERFLOW}}
\index{CSR_OVERFLOW@{CSR\_\-OVERFLOW}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-OVERFLOW\ 0x20}\label{h8_8h_a41}




Definition at line 180 of file h8.h.\index{h8.h@{h8.h}!CSR_TOGGLE_ON_A@{CSR\_\-TOGGLE\_\-ON\_\-A}}
\index{CSR_TOGGLE_ON_A@{CSR\_\-TOGGLE\_\-ON\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-TOGGLE\_\-ON\_\-A\ 0x03}\label{h8_8h_a49}




Definition at line 190 of file h8.h.\index{h8.h@{h8.h}!CSR_TOGGLE_ON_B@{CSR\_\-TOGGLE\_\-ON\_\-B}}
\index{CSR_TOGGLE_ON_B@{CSR\_\-TOGGLE\_\-ON\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define CSR\_\-TOGGLE\_\-ON\_\-B\ 0x0c}\label{h8_8h_a45}




Definition at line 185 of file h8.h.\index{h8.h@{h8.h}!SCR_CLOCK_OUT@{SCR\_\-CLOCK\_\-OUT}}
\index{SCR_CLOCK_OUT@{SCR\_\-CLOCK\_\-OUT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-CLOCK\_\-OUT\ 0x01}\label{h8_8h_a72}




Definition at line 245 of file h8.h.\index{h8.h@{h8.h}!SCR_EXT_CLOCK@{SCR\_\-EXT\_\-CLOCK}}
\index{SCR_EXT_CLOCK@{SCR\_\-EXT\_\-CLOCK}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-EXT\_\-CLOCK\ 0x02}\label{h8_8h_a71}




Definition at line 244 of file h8.h.\index{h8.h@{h8.h}!SCR_INT_CLOCK@{SCR\_\-INT\_\-CLOCK}}
\index{SCR_INT_CLOCK@{SCR\_\-INT\_\-CLOCK}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-INT\_\-CLOCK\ 0x00}\label{h8_8h_a70}




Definition at line 243 of file h8.h.\index{h8.h@{h8.h}!SCR_MP_IRQ@{SCR\_\-MP\_\-IRQ}}
\index{SCR_MP_IRQ@{SCR\_\-MP\_\-IRQ}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-MP\_\-IRQ\ 0x08}\label{h8_8h_a68}




Definition at line 241 of file h8.h.\index{h8.h@{h8.h}!SCR_RECEIVE@{SCR\_\-RECEIVE}}
\index{SCR_RECEIVE@{SCR\_\-RECEIVE}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-RECEIVE\ 0x10}\label{h8_8h_a67}




Definition at line 240 of file h8.h.\index{h8.h@{h8.h}!SCR_RX_IRQ@{SCR\_\-RX\_\-IRQ}}
\index{SCR_RX_IRQ@{SCR\_\-RX\_\-IRQ}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-RX\_\-IRQ\ 0x40}\label{h8_8h_a65}




Definition at line 238 of file h8.h.\index{h8.h@{h8.h}!SCR_TE_IRQ@{SCR\_\-TE\_\-IRQ}}
\index{SCR_TE_IRQ@{SCR\_\-TE\_\-IRQ}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-TE\_\-IRQ\ 0x04}\label{h8_8h_a69}




Definition at line 242 of file h8.h.\index{h8.h@{h8.h}!SCR_TRANSMIT@{SCR\_\-TRANSMIT}}
\index{SCR_TRANSMIT@{SCR\_\-TRANSMIT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-TRANSMIT\ 0x20}\label{h8_8h_a66}




Definition at line 239 of file h8.h.\index{h8.h@{h8.h}!SCR_TX_IRQ@{SCR\_\-TX\_\-IRQ}}
\index{SCR_TX_IRQ@{SCR\_\-TX\_\-IRQ}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SCR\_\-TX\_\-IRQ\ 0x80}\label{h8_8h_a64}




Definition at line 237 of file h8.h.\index{h8.h@{h8.h}!SMR_1STOP@{SMR\_\-1STOP}}
\index{SMR_1STOP@{SMR\_\-1STOP}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-1STOP\ 0x00}\label{h8_8h_a57}




Definition at line 227 of file h8.h.\index{h8.h@{h8.h}!SMR_2STOP@{SMR\_\-2STOP}}
\index{SMR_2STOP@{SMR\_\-2STOP}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-2STOP\ 0x08}\label{h8_8h_a58}




Definition at line 228 of file h8.h.\index{h8.h@{h8.h}!SMR_7BIT@{SMR\_\-7BIT}}
\index{SMR_7BIT@{SMR\_\-7BIT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-7BIT\ 0x40}\label{h8_8h_a52}




Definition at line 222 of file h8.h.\index{h8.h@{h8.h}!SMR_8BIT@{SMR\_\-8BIT}}
\index{SMR_8BIT@{SMR\_\-8BIT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-8BIT\ 0x00}\label{h8_8h_a53}




Definition at line 223 of file h8.h.\index{h8.h@{h8.h}!SMR_ASYNC@{SMR\_\-ASYNC}}
\index{SMR_ASYNC@{SMR\_\-ASYNC}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-ASYNC\ 0x00}\label{h8_8h_a51}




Definition at line 221 of file h8.h.\index{h8.h@{h8.h}!SMR_CLOCK@{SMR\_\-CLOCK}}
\index{SMR_CLOCK@{SMR\_\-CLOCK}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-CLOCK\ 0x00}\label{h8_8h_a60}




Definition at line 231 of file h8.h.\index{h8.h@{h8.h}!SMR_CLOCK_16@{SMR\_\-CLOCK\_\-16}}
\index{SMR_CLOCK_16@{SMR\_\-CLOCK\_\-16}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-CLOCK\_\-16\ 0x02}\label{h8_8h_a62}




Definition at line 233 of file h8.h.\index{h8.h@{h8.h}!SMR_CLOCK_4@{SMR\_\-CLOCK\_\-4}}
\index{SMR_CLOCK_4@{SMR\_\-CLOCK\_\-4}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-CLOCK\_\-4\ 0x01}\label{h8_8h_a61}




Definition at line 232 of file h8.h.\index{h8.h@{h8.h}!SMR_CLOCK_64@{SMR\_\-CLOCK\_\-64}}
\index{SMR_CLOCK_64@{SMR\_\-CLOCK\_\-64}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-CLOCK\_\-64\ 0x03}\label{h8_8h_a63}




Definition at line 234 of file h8.h.\index{h8.h@{h8.h}!SMR_MP@{SMR\_\-MP}}
\index{SMR_MP@{SMR\_\-MP}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-MP\ 0x04}\label{h8_8h_a59}




Definition at line 229 of file h8.h.\index{h8.h@{h8.h}!SMR_P_EVEN@{SMR\_\-P\_\-EVEN}}
\index{SMR_P_EVEN@{SMR\_\-P\_\-EVEN}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-P\_\-EVEN\ 0x20}\label{h8_8h_a55}




Definition at line 225 of file h8.h.\index{h8.h@{h8.h}!SMR_P_NONE@{SMR\_\-P\_\-NONE}}
\index{SMR_P_NONE@{SMR\_\-P\_\-NONE}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-P\_\-NONE\ 0x00}\label{h8_8h_a54}




Definition at line 224 of file h8.h.\index{h8.h@{h8.h}!SMR_P_ODD@{SMR\_\-P\_\-ODD}}
\index{SMR_P_ODD@{SMR\_\-P\_\-ODD}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-P\_\-ODD\ 0x30}\label{h8_8h_a56}




Definition at line 226 of file h8.h.\index{h8.h@{h8.h}!SMR_SYNC@{SMR\_\-SYNC}}
\index{SMR_SYNC@{SMR\_\-SYNC}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SMR\_\-SYNC\ 0x80}\label{h8_8h_a50}




Definition at line 220 of file h8.h.\index{h8.h@{h8.h}!SSR_ERRORS@{SSR\_\-ERRORS}}
\index{SSR_ERRORS@{SSR\_\-ERRORS}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-ERRORS\ 0x38}\label{h8_8h_a78}




Definition at line 253 of file h8.h.\index{h8.h@{h8.h}!SSR_FRAMING_ERR@{SSR\_\-FRAMING\_\-ERR}}
\index{SSR_FRAMING_ERR@{SSR\_\-FRAMING\_\-ERR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-FRAMING\_\-ERR\ 0x10}\label{h8_8h_a76}




Definition at line 251 of file h8.h.\index{h8.h@{h8.h}!SSR_MP@{SSR\_\-MP}}
\index{SSR_MP@{SSR\_\-MP}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-MP\ 0x02}\label{h8_8h_a80}




Definition at line 255 of file h8.h.\index{h8.h@{h8.h}!SSR_MP_TRANSFER@{SSR\_\-MP\_\-TRANSFER}}
\index{SSR_MP_TRANSFER@{SSR\_\-MP\_\-TRANSFER}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-MP\_\-TRANSFER\ 0x01}\label{h8_8h_a81}




Definition at line 256 of file h8.h.\index{h8.h@{h8.h}!SSR_OVERRUN_ERR@{SSR\_\-OVERRUN\_\-ERR}}
\index{SSR_OVERRUN_ERR@{SSR\_\-OVERRUN\_\-ERR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-OVERRUN\_\-ERR\ 0x20}\label{h8_8h_a75}




Definition at line 250 of file h8.h.\index{h8.h@{h8.h}!SSR_PARITY_ERR@{SSR\_\-PARITY\_\-ERR}}
\index{SSR_PARITY_ERR@{SSR\_\-PARITY\_\-ERR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-PARITY\_\-ERR\ 0x08}\label{h8_8h_a77}




Definition at line 252 of file h8.h.\index{h8.h@{h8.h}!SSR_RECV_FULL@{SSR\_\-RECV\_\-FULL}}
\index{SSR_RECV_FULL@{SSR\_\-RECV\_\-FULL}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-RECV\_\-FULL\ 0x40}\label{h8_8h_a74}




Definition at line 249 of file h8.h.\index{h8.h@{h8.h}!SSR_TRANS_EMPTY@{SSR\_\-TRANS\_\-EMPTY}}
\index{SSR_TRANS_EMPTY@{SSR\_\-TRANS\_\-EMPTY}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-TRANS\_\-EMPTY\ 0x80}\label{h8_8h_a73}




Definition at line 248 of file h8.h.\index{h8.h@{h8.h}!SSR_TRANS_END@{SSR\_\-TRANS\_\-END}}
\index{SSR_TRANS_END@{SSR\_\-TRANS\_\-END}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SSR\_\-TRANS\_\-END\ 0x04}\label{h8_8h_a79}




Definition at line 254 of file h8.h.\index{h8.h@{h8.h}!SYSCR_SOFTWARE_STANDBY@{SYSCR\_\-SOFTWARE\_\-STANDBY}}
\index{SYSCR_SOFTWARE_STANDBY@{SYSCR\_\-SOFTWARE\_\-STANDBY}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define SYSCR\_\-SOFTWARE\_\-STANDBY\ 0x80}\label{h8_8h_a100}




Definition at line 361 of file h8.h.\index{h8.h@{h8.h}!TCR_A_RISING@{TCR\_\-A\_\-RISING}}
\index{TCR_A_RISING@{TCR\_\-A\_\-RISING}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-A\_\-RISING\ 0x80}\label{h8_8h_a16}




Definition at line 98 of file h8.h.\index{h8.h@{h8.h}!TCR_B_RISING@{TCR\_\-B\_\-RISING}}
\index{TCR_B_RISING@{TCR\_\-B\_\-RISING}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-B\_\-RISING\ 0x40}\label{h8_8h_a17}




Definition at line 99 of file h8.h.\index{h8.h@{h8.h}!TCR_BUFFER_A@{TCR\_\-BUFFER\_\-A}}
\index{TCR_BUFFER_A@{TCR\_\-BUFFER\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-BUFFER\_\-A\ 0x08}\label{h8_8h_a20}




Definition at line 102 of file h8.h.\index{h8.h@{h8.h}!TCR_BUFFER_B@{TCR\_\-BUFFER\_\-B}}
\index{TCR_BUFFER_B@{TCR\_\-BUFFER\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-BUFFER\_\-B\ 0x04}\label{h8_8h_a21}




Definition at line 103 of file h8.h.\index{h8.h@{h8.h}!TCR_C_RISING@{TCR\_\-C\_\-RISING}}
\index{TCR_C_RISING@{TCR\_\-C\_\-RISING}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-C\_\-RISING\ 0x20}\label{h8_8h_a18}




Definition at line 100 of file h8.h.\index{h8.h@{h8.h}!TCR_CLOCK_2@{TCR\_\-CLOCK\_\-2}}
\index{TCR_CLOCK_2@{TCR\_\-CLOCK\_\-2}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-CLOCK\_\-2\ 0x00}\label{h8_8h_a22}




Definition at line 104 of file h8.h.\index{h8.h@{h8.h}!TCR_CLOCK_32@{TCR\_\-CLOCK\_\-32}}
\index{TCR_CLOCK_32@{TCR\_\-CLOCK\_\-32}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-CLOCK\_\-32\ 0x02}\label{h8_8h_a24}




Definition at line 106 of file h8.h.\index{h8.h@{h8.h}!TCR_CLOCK_8@{TCR\_\-CLOCK\_\-8}}
\index{TCR_CLOCK_8@{TCR\_\-CLOCK\_\-8}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-CLOCK\_\-8\ 0x01}\label{h8_8h_a23}




Definition at line 105 of file h8.h.\index{h8.h@{h8.h}!TCR_CLOCK_EXT@{TCR\_\-CLOCK\_\-EXT}}
\index{TCR_CLOCK_EXT@{TCR\_\-CLOCK\_\-EXT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-CLOCK\_\-EXT\ 0x03}\label{h8_8h_a25}




Definition at line 107 of file h8.h.\index{h8.h@{h8.h}!TCR_D_RISING@{TCR\_\-D\_\-RISING}}
\index{TCR_D_RISING@{TCR\_\-D\_\-RISING}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCR\_\-D\_\-RISING\ 0x10}\label{h8_8h_a19}




Definition at line 101 of file h8.h.\index{h8.h@{h8.h}!TCSR_ICA@{TCSR\_\-ICA}}
\index{TCSR_ICA@{TCSR\_\-ICA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-ICA\ 0x80}\label{h8_8h_a8}




Definition at line 86 of file h8.h.\index{h8.h@{h8.h}!TCSR_ICB@{TCSR\_\-ICB}}
\index{TCSR_ICB@{TCSR\_\-ICB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-ICB\ 0x40}\label{h8_8h_a9}




Definition at line 87 of file h8.h.\index{h8.h@{h8.h}!TCSR_ICC@{TCSR\_\-ICC}}
\index{TCSR_ICC@{TCSR\_\-ICC}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-ICC\ 0x20}\label{h8_8h_a10}




Definition at line 88 of file h8.h.\index{h8.h@{h8.h}!TCSR_ICD@{TCSR\_\-ICD}}
\index{TCSR_ICD@{TCSR\_\-ICD}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-ICD\ 0x10}\label{h8_8h_a11}




Definition at line 89 of file h8.h.\index{h8.h@{h8.h}!TCSR_OCA@{TCSR\_\-OCA}}
\index{TCSR_OCA@{TCSR\_\-OCA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-OCA\ 0x08}\label{h8_8h_a12}




Definition at line 90 of file h8.h.\index{h8.h@{h8.h}!TCSR_OCB@{TCSR\_\-OCB}}
\index{TCSR_OCB@{TCSR\_\-OCB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-OCB\ 0x04}\label{h8_8h_a13}




Definition at line 91 of file h8.h.\index{h8.h@{h8.h}!TCSR_OF@{TCSR\_\-OF}}
\index{TCSR_OF@{TCSR\_\-OF}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-OF\ 0x02}\label{h8_8h_a14}




Definition at line 92 of file h8.h.\index{h8.h@{h8.h}!TCSR_RESET_ON_A@{TCSR\_\-RESET\_\-ON\_\-A}}
\index{TCSR_RESET_ON_A@{TCSR\_\-RESET\_\-ON\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TCSR\_\-RESET\_\-ON\_\-A\ 0x01}\label{h8_8h_a15}




Definition at line 93 of file h8.h.\index{h8.h@{h8.h}!TIER_ENABLE_ICA@{TIER\_\-ENABLE\_\-ICA}}
\index{TIER_ENABLE_ICA@{TIER\_\-ENABLE\_\-ICA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-ENABLE\_\-ICA\ 0x80}\label{h8_8h_a0}




Definition at line 74 of file h8.h.\index{h8.h@{h8.h}!TIER_ENABLE_ICB@{TIER\_\-ENABLE\_\-ICB}}
\index{TIER_ENABLE_ICB@{TIER\_\-ENABLE\_\-ICB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-ENABLE\_\-ICB\ 0x40}\label{h8_8h_a1}




Definition at line 75 of file h8.h.\index{h8.h@{h8.h}!TIER_ENABLE_ICC@{TIER\_\-ENABLE\_\-ICC}}
\index{TIER_ENABLE_ICC@{TIER\_\-ENABLE\_\-ICC}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-ENABLE\_\-ICC\ 0x20}\label{h8_8h_a2}




Definition at line 76 of file h8.h.\index{h8.h@{h8.h}!TIER_ENABLE_ICD@{TIER\_\-ENABLE\_\-ICD}}
\index{TIER_ENABLE_ICD@{TIER\_\-ENABLE\_\-ICD}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-ENABLE\_\-ICD\ 0x10}\label{h8_8h_a3}




Definition at line 77 of file h8.h.\index{h8.h@{h8.h}!TIER_ENABLE_OCA@{TIER\_\-ENABLE\_\-OCA}}
\index{TIER_ENABLE_OCA@{TIER\_\-ENABLE\_\-OCA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-ENABLE\_\-OCA\ 0x08}\label{h8_8h_a4}




Definition at line 78 of file h8.h.\index{h8.h@{h8.h}!TIER_ENABLE_OCB@{TIER\_\-ENABLE\_\-OCB}}
\index{TIER_ENABLE_OCB@{TIER\_\-ENABLE\_\-OCB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-ENABLE\_\-OCB\ 0x04}\label{h8_8h_a5}




Definition at line 79 of file h8.h.\index{h8.h@{h8.h}!TIER_ENABLE_OF@{TIER\_\-ENABLE\_\-OF}}
\index{TIER_ENABLE_OF@{TIER\_\-ENABLE\_\-OF}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-ENABLE\_\-OF\ 0x02}\label{h8_8h_a6}




Definition at line 80 of file h8.h.\index{h8.h@{h8.h}!TIER_RESERVED@{TIER\_\-RESERVED}}
\index{TIER_RESERVED@{TIER\_\-RESERVED}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TIER\_\-RESERVED\ 0x01}\label{h8_8h_a7}




Definition at line 81 of file h8.h.\index{h8.h@{h8.h}!TOCR_ENABLE_A@{TOCR\_\-ENABLE\_\-A}}
\index{TOCR_ENABLE_A@{TOCR\_\-ENABLE\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TOCR\_\-ENABLE\_\-A\ 0x08}\label{h8_8h_a28}




Definition at line 114 of file h8.h.\index{h8.h@{h8.h}!TOCR_ENABLE_B@{TOCR\_\-ENABLE\_\-B}}
\index{TOCR_ENABLE_B@{TOCR\_\-ENABLE\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TOCR\_\-ENABLE\_\-B\ 0x04}\label{h8_8h_a29}




Definition at line 115 of file h8.h.\index{h8.h@{h8.h}!TOCR_HIGH_LEVEL_A@{TOCR\_\-HIGH\_\-LEVEL\_\-A}}
\index{TOCR_HIGH_LEVEL_A@{TOCR\_\-HIGH\_\-LEVEL\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TOCR\_\-HIGH\_\-LEVEL\_\-A\ 0x02}\label{h8_8h_a30}




Definition at line 116 of file h8.h.\index{h8.h@{h8.h}!TOCR_HIGH_LEVEL_B@{TOCR\_\-HIGH\_\-LEVEL\_\-B}}
\index{TOCR_HIGH_LEVEL_B@{TOCR\_\-HIGH\_\-LEVEL\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TOCR\_\-HIGH\_\-LEVEL\_\-B\ 0x01}\label{h8_8h_a31}




Definition at line 117 of file h8.h.\index{h8.h@{h8.h}!TOCR_OCRA@{TOCR\_\-OCRA}}
\index{TOCR_OCRA@{TOCR\_\-OCRA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TOCR\_\-OCRA\ 0x00}\label{h8_8h_a26}




Definition at line 112 of file h8.h.\index{h8.h@{h8.h}!TOCR_OCRB@{TOCR\_\-OCRB}}
\index{TOCR_OCRB@{TOCR\_\-OCRB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define TOCR\_\-OCRB\ 0x10}\label{h8_8h_a27}




Definition at line 113 of file h8.h.\index{h8.h@{h8.h}!WDT_CNT_CLEAR@{WDT\_\-CNT\_\-CLEAR}}
\index{WDT_CNT_CLEAR@{WDT\_\-CNT\_\-CLEAR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CNT\_\-CLEAR\ (0x0000)}\label{h8_8h_a116}




Definition at line 447 of file h8.h.\index{h8.h@{h8.h}!WDT_CNT_MSEC_64@{WDT\_\-CNT\_\-MSEC\_\-64}}
\index{WDT_CNT_MSEC_64@{WDT\_\-CNT\_\-MSEC\_\-64}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CNT\_\-MSEC\_\-64\ (0x0006)}\label{h8_8h_a117}




Definition at line 448 of file h8.h.\index{h8.h@{h8.h}!WDT_CNT_PASSWORD@{WDT\_\-CNT\_\-PASSWORD}}
\index{WDT_CNT_PASSWORD@{WDT\_\-CNT\_\-PASSWORD}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CNT\_\-PASSWORD\ (0x5A00)}\label{h8_8h_a115}




Definition at line 446 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_128@{WDT\_\-CSR\_\-CLOCK\_\-128}}
\index{WDT_CSR_CLOCK_128@{WDT\_\-CSR\_\-CLOCK\_\-128}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-128\ (0x0003)}\label{h8_8h_a110}




Definition at line 437 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_2@{WDT\_\-CSR\_\-CLOCK\_\-2}}
\index{WDT_CSR_CLOCK_2@{WDT\_\-CSR\_\-CLOCK\_\-2}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-2\ (0x0000)}\label{h8_8h_a107}




Definition at line 434 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_2048@{WDT\_\-CSR\_\-CLOCK\_\-2048}}
\index{WDT_CSR_CLOCK_2048@{WDT\_\-CSR\_\-CLOCK\_\-2048}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-2048\ (0x0006)}\label{h8_8h_a113}




Definition at line 440 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_256@{WDT\_\-CSR\_\-CLOCK\_\-256}}
\index{WDT_CSR_CLOCK_256@{WDT\_\-CSR\_\-CLOCK\_\-256}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-256\ (0x0004)}\label{h8_8h_a111}




Definition at line 438 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_32@{WDT\_\-CSR\_\-CLOCK\_\-32}}
\index{WDT_CSR_CLOCK_32@{WDT\_\-CSR\_\-CLOCK\_\-32}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-32\ (0x0001)}\label{h8_8h_a108}




Definition at line 435 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_4096@{WDT\_\-CSR\_\-CLOCK\_\-4096}}
\index{WDT_CSR_CLOCK_4096@{WDT\_\-CSR\_\-CLOCK\_\-4096}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-4096\ (0x0007)}\label{h8_8h_a114}




Definition at line 441 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_512@{WDT\_\-CSR\_\-CLOCK\_\-512}}
\index{WDT_CSR_CLOCK_512@{WDT\_\-CSR\_\-CLOCK\_\-512}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-512\ (0x0005)}\label{h8_8h_a112}




Definition at line 439 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_CLOCK_64@{WDT\_\-CSR\_\-CLOCK\_\-64}}
\index{WDT_CSR_CLOCK_64@{WDT\_\-CSR\_\-CLOCK\_\-64}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-CLOCK\_\-64\ (0x0002)}\label{h8_8h_a109}




Definition at line 436 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_ENABLE@{WDT\_\-CSR\_\-ENABLE}}
\index{WDT_CSR_ENABLE@{WDT\_\-CSR\_\-ENABLE}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-ENABLE\ (0x0020)}\label{h8_8h_a102}




Definition at line 429 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_MODE_OVERFLOW@{WDT\_\-CSR\_\-MODE\_\-OVERFLOW}}
\index{WDT_CSR_MODE_OVERFLOW@{WDT\_\-CSR\_\-MODE\_\-OVERFLOW}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-MODE\_\-OVERFLOW\ (0x0000)}\label{h8_8h_a104}




Definition at line 431 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_MODE_WATCHDOG@{WDT\_\-CSR\_\-MODE\_\-WATCHDOG}}
\index{WDT_CSR_MODE_WATCHDOG@{WDT\_\-CSR\_\-MODE\_\-WATCHDOG}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-MODE\_\-WATCHDOG\ (0x0040)}\label{h8_8h_a103}




Definition at line 430 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_PASSWORD@{WDT\_\-CSR\_\-PASSWORD}}
\index{WDT_CSR_PASSWORD@{WDT\_\-CSR\_\-PASSWORD}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-PASSWORD\ (0x\-A500)}\label{h8_8h_a101}




Definition at line 428 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_WATCHDOG_NMI@{WDT\_\-CSR\_\-WATCHDOG\_\-NMI}}
\index{WDT_CSR_WATCHDOG_NMI@{WDT\_\-CSR\_\-WATCHDOG\_\-NMI}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-WATCHDOG\_\-NMI\ (0x0000)}\label{h8_8h_a105}




Definition at line 432 of file h8.h.\index{h8.h@{h8.h}!WDT_CSR_WATCHDOG_RES@{WDT\_\-CSR\_\-WATCHDOG\_\-RES}}
\index{WDT_CSR_WATCHDOG_RES@{WDT\_\-CSR\_\-WATCHDOG\_\-RES}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}\#define WDT\_\-CSR\_\-WATCHDOG\_\-RES\ (0x0008)}\label{h8_8h_a106}




Definition at line 433 of file h8.h.

\subsection{Variable Documentation}
\index{h8.h@{h8.h}!AD_A@{AD\_\-A}}
\index{AD_A@{AD\_\-A}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf AD\_\-A}}\label{h8_8h_a155}


A/D converter data register A. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!AD_A_H@{AD\_\-A\_\-H}}
\index{AD_A_H@{AD\_\-A\_\-H}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-A\_\-H}}\label{h8_8h_a147}


A/D converter data register A high. 

\index{h8.h@{h8.h}!AD_A_L@{AD\_\-A\_\-L}}
\index{AD_A_L@{AD\_\-A\_\-L}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-A\_\-L}}\label{h8_8h_a148}


A/D converter data register A low. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!AD_B@{AD\_\-B}}
\index{AD_B@{AD\_\-B}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf AD\_\-B}}\label{h8_8h_a156}


A/D converter data register B. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!AD_B_H@{AD\_\-B\_\-H}}
\index{AD_B_H@{AD\_\-B\_\-H}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-B\_\-H}}\label{h8_8h_a149}


A/D converter data register B high. 

\index{h8.h@{h8.h}!AD_B_L@{AD\_\-B\_\-L}}
\index{AD_B_L@{AD\_\-B\_\-L}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-B\_\-L}}\label{h8_8h_a150}


A/D converter data register B low. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!AD_C@{AD\_\-C}}
\index{AD_C@{AD\_\-C}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf AD\_\-C}}\label{h8_8h_a157}


A/D converter data register C. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!AD_C_H@{AD\_\-C\_\-H}}
\index{AD_C_H@{AD\_\-C\_\-H}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-C\_\-H}}\label{h8_8h_a151}


A/D converter data register C high. 

\index{h8.h@{h8.h}!AD_C_L@{AD\_\-C\_\-L}}
\index{AD_C_L@{AD\_\-C\_\-L}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-C\_\-L}}\label{h8_8h_a152}


A/D converter data register C low. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!AD_CR@{AD\_\-CR}}
\index{AD_CR@{AD\_\-CR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf AD\_\-CR}}\label{h8_8h_a160}


A/D converter control register. 

\index{h8.h@{h8.h}!AD_CSR@{AD\_\-CSR}}
\index{AD_CSR@{AD\_\-CSR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-CSR}}\label{h8_8h_a159}


A/D converter control / status register. 

\index{h8.h@{h8.h}!AD_D@{AD\_\-D}}
\index{AD_D@{AD\_\-D}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf AD\_\-D}}\label{h8_8h_a158}


A/D converter data register D. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!AD_D_H@{AD\_\-D\_\-H}}
\index{AD_D_H@{AD\_\-D\_\-H}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-D\_\-H}}\label{h8_8h_a153}


A/D converter data register D high. 

\index{h8.h@{h8.h}!AD_D_L@{AD\_\-D\_\-L}}
\index{AD_D_L@{AD\_\-D\_\-L}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf AD\_\-D\_\-L}}\label{h8_8h_a154}


A/D converter data register D low. 

bits 0..5 reserved, probably zero \index{h8.h@{h8.h}!PORT1@{PORT1}}
\index{PORT1@{PORT1}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf PORT1}}\label{h8_8h_a166}


port 1 I/O register 

\index{h8.h@{h8.h}!PORT1_DDR@{PORT1\_\-DDR}}
\index{PORT1_DDR@{PORT1\_\-DDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT1\_\-DDR}}\label{h8_8h_a165}


port 1 data direction register 

\index{h8.h@{h8.h}!PORT1_PCR@{PORT1\_\-PCR}}
\index{PORT1_PCR@{PORT1\_\-PCR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT1\_\-PCR}}\label{h8_8h_a162}


port 1 input pull-up control register 

\index{h8.h@{h8.h}!PORT2@{PORT2}}
\index{PORT2@{PORT2}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf PORT2}}\label{h8_8h_a168}


port 2 I/O register 

\index{h8.h@{h8.h}!PORT2_DDR@{PORT2\_\-DDR}}
\index{PORT2_DDR@{PORT2\_\-DDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT2\_\-DDR}}\label{h8_8h_a167}


port 2 data direction register 

\index{h8.h@{h8.h}!PORT2_PCR@{PORT2\_\-PCR}}
\index{PORT2_PCR@{PORT2\_\-PCR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT2\_\-PCR}}\label{h8_8h_a163}


port 2 input pull-up control register 

\index{h8.h@{h8.h}!PORT3@{PORT3}}
\index{PORT3@{PORT3}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf PORT3}}\label{h8_8h_a170}


port 3 I/O register 

\index{h8.h@{h8.h}!PORT3_DDR@{PORT3\_\-DDR}}
\index{PORT3_DDR@{PORT3\_\-DDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT3\_\-DDR}}\label{h8_8h_a169}


port 3 data direction register 

\index{h8.h@{h8.h}!PORT3_PCR@{PORT3\_\-PCR}}
\index{PORT3_PCR@{PORT3\_\-PCR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT3\_\-PCR}}\label{h8_8h_a164}


port 3 input pull-up control register 

\index{h8.h@{h8.h}!PORT4@{PORT4}}
\index{PORT4@{PORT4}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf PORT4}}\label{h8_8h_a172}


port 4 I/O register 

\index{h8.h@{h8.h}!PORT4_DDR@{PORT4\_\-DDR}}
\index{PORT4_DDR@{PORT4\_\-DDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT4\_\-DDR}}\label{h8_8h_a171}


port 4 data direction register 

\index{h8.h@{h8.h}!PORT5@{PORT5}}
\index{PORT5@{PORT5}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf PORT5}}\label{h8_8h_a174}


port 5 I/O register 

\index{h8.h@{h8.h}!PORT5_DDR@{PORT5\_\-DDR}}
\index{PORT5_DDR@{PORT5\_\-DDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT5\_\-DDR}}\label{h8_8h_a173}


port 5 data direction register 

\index{h8.h@{h8.h}!PORT6@{PORT6}}
\index{PORT6@{PORT6}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf PORT6}}\label{h8_8h_a176}


port 6 I/O register 

\index{h8.h@{h8.h}!PORT6_DDR@{PORT6\_\-DDR}}
\index{PORT6_DDR@{PORT6\_\-DDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf PORT6\_\-DDR}}\label{h8_8h_a175}


port 6 data direction register 



Referenced by i2c\_\-read\_\-ack(), and lcd\_\-init().\index{h8.h@{h8.h}!PORT7@{PORT7}}
\index{PORT7@{PORT7}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf PORT7}}\label{h8_8h_a177}


port 7 input register 

\index{h8.h@{h8.h}!S_BRR@{S\_\-BRR}}
\index{S_BRR@{S\_\-BRR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf S\_\-BRR}}\label{h8_8h_a145}


serial baud rate register 

\index{h8.h@{h8.h}!S_CR@{S\_\-CR}}
\index{S_CR@{S\_\-CR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf S\_\-CR}}\label{h8_8h_a143}


serial control register 

\index{h8.h@{h8.h}!S_MR@{S\_\-MR}}
\index{S_MR@{S\_\-MR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf S\_\-MR}}\label{h8_8h_a142}


serial mode register 

\index{h8.h@{h8.h}!S_RDR@{S\_\-RDR}}
\index{S_RDR@{S\_\-RDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf S\_\-RDR}}\label{h8_8h_a140}


serial receive data register 

\index{h8.h@{h8.h}!S_SR@{S\_\-SR}}
\index{S_SR@{S\_\-SR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf S\_\-SR}}\label{h8_8h_a144}


serial status register 

\index{h8.h@{h8.h}!S_TCR@{S\_\-TCR}}
\index{S_TCR@{S\_\-TCR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf S\_\-TCR}}\label{h8_8h_a146}


serial / timer control register 

\index{h8.h@{h8.h}!S_TDR@{S\_\-TDR}}
\index{S_TDR@{S\_\-TDR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf S\_\-TDR}}\label{h8_8h_a141}


serial transmit data register 

\index{h8.h@{h8.h}!STCR@{STCR}}
\index{STCR@{STCR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf STCR}}\label{h8_8h_a129}


serial / timer control register 

\index{h8.h@{h8.h}!SYSCR@{SYSCR}}
\index{SYSCR@{SYSCR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf SYSCR}}\label{h8_8h_a161}


system control register 

\index{h8.h@{h8.h}!T0_CNT@{T0\_\-CNT}}
\index{T0_CNT@{T0\_\-CNT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf T0\_\-CNT}}\label{h8_8h_a134}


timer 0 counter register 

\index{h8.h@{h8.h}!T0_CORA@{T0\_\-CORA}}
\index{T0_CORA@{T0\_\-CORA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T0\_\-CORA}}\label{h8_8h_a132}


timer 0 constant A register 

\index{h8.h@{h8.h}!T0_CORB@{T0\_\-CORB}}
\index{T0_CORB@{T0\_\-CORB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T0\_\-CORB}}\label{h8_8h_a133}


timer 0 constant B register 

\index{h8.h@{h8.h}!T0_CR@{T0\_\-CR}}
\index{T0_CR@{T0\_\-CR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T0\_\-CR}}\label{h8_8h_a130}


timer 0 control register 

\index{h8.h@{h8.h}!T0_CSR@{T0\_\-CSR}}
\index{T0_CSR@{T0\_\-CSR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf T0\_\-CSR}}\label{h8_8h_a131}


timer 0 control / status register 

\index{h8.h@{h8.h}!T1_CNT@{T1\_\-CNT}}
\index{T1_CNT@{T1\_\-CNT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf T1\_\-CNT}}\label{h8_8h_a139}


timer 1 counter register 

\index{h8.h@{h8.h}!T1_CORA@{T1\_\-CORA}}
\index{T1_CORA@{T1\_\-CORA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T1\_\-CORA}}\label{h8_8h_a137}


timer 1 constant A register 

\index{h8.h@{h8.h}!T1_CORB@{T1\_\-CORB}}
\index{T1_CORB@{T1\_\-CORB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T1\_\-CORB}}\label{h8_8h_a138}


timer 1 constant B register 

\index{h8.h@{h8.h}!T1_CR@{T1\_\-CR}}
\index{T1_CR@{T1\_\-CR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T1\_\-CR}}\label{h8_8h_a135}


timer 1 control register 

\index{h8.h@{h8.h}!T1_CSR@{T1\_\-CSR}}
\index{T1_CSR@{T1\_\-CSR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf T1\_\-CSR}}\label{h8_8h_a136}


timer 1 control / status register 

\index{h8.h@{h8.h}!T_CNT@{T\_\-CNT}}
\index{T_CNT@{T\_\-CNT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf T\_\-CNT}}\label{h8_8h_a120}


16-bit timer count register 

\index{h8.h@{h8.h}!T_CR@{T\_\-CR}}
\index{T_CR@{T\_\-CR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T\_\-CR}}\label{h8_8h_a123}


16-bit timer control register 

\index{h8.h@{h8.h}!T_CSR@{T\_\-CSR}}
\index{T_CSR@{T\_\-CSR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf T\_\-CSR}}\label{h8_8h_a119}


16-bit timer control / status register 

\index{h8.h@{h8.h}!T_ICRA@{T\_\-ICRA}}
\index{T_ICRA@{T\_\-ICRA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf T\_\-ICRA}}\label{h8_8h_a125}


16-bit timer input capture A register 

\index{h8.h@{h8.h}!T_ICRB@{T\_\-ICRB}}
\index{T_ICRB@{T\_\-ICRB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf T\_\-ICRB}}\label{h8_8h_a126}


16-bit timer input capture B register 

\index{h8.h@{h8.h}!T_ICRC@{T\_\-ICRC}}
\index{T_ICRC@{T\_\-ICRC}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf T\_\-ICRC}}\label{h8_8h_a127}


16-bit timer input capture C register 

\index{h8.h@{h8.h}!T_ICRD@{T\_\-ICRD}}
\index{T_ICRD@{T\_\-ICRD}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned {\bf T\_\-ICRD}}\label{h8_8h_a128}


16-bit timer input capture D register 

\index{h8.h@{h8.h}!T_IER@{T\_\-IER}}
\index{T_IER@{T\_\-IER}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T\_\-IER}}\label{h8_8h_a118}


16-bit timer interrupt enable register 

\index{h8.h@{h8.h}!T_OCR@{T\_\-OCR}}
\index{T_OCR@{T\_\-OCR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned char {\bf T\_\-OCR}}\label{h8_8h_a124}


16-bit timer output control register 

\index{h8.h@{h8.h}!T_OCRA@{T\_\-OCRA}}
\index{T_OCRA@{T\_\-OCRA}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned {\bf T\_\-OCRA}}\label{h8_8h_a121}


16-bit timer output compare register A 

\index{h8.h@{h8.h}!T_OCRB@{T\_\-OCRB}}
\index{T_OCRB@{T\_\-OCRB}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}unsigned {\bf T\_\-OCRB}}\label{h8_8h_a122}


16-bit timer output compare register B 

\index{h8.h@{h8.h}!WDT_CNT@{WDT\_\-CNT}}
\index{WDT_CNT@{WDT\_\-CNT}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned char {\bf WDT\_\-CNT}}\label{h8_8h_a179}


watch dog timer counter register 

\index{h8.h@{h8.h}!WDT_CSR@{WDT\_\-CSR}}
\index{WDT_CSR@{WDT\_\-CSR}!h8.h@{h8.h}}
\subsubsection{\setlength{\rightskip}{0pt plus 5cm}volatile unsigned int {\bf WDT\_\-CSR}}\label{h8_8h_a178}


watch dog timer control register 

