User/Supervisor Modes, Intel Style

As is apparent now from the various presentations we have had, most clearly in Debzani's presentation on virtual memory, the Intel architecture does not have a user/supervisor bit that provides the status of the processor.  Still, this capability must be present, and it is in a different form.  Segments are designated as having one of four priority levels, 0, 1, 2, 3.  That is, the priority is associated with the code in a segment of memory rather than with a state of the processor.  So, during decoding a privileged instruction, the processor would check the privilege bits of the segment descriptor for the code being executed and raise an exception if the privilege level is not high enough for that instruction.

Since UNIX has traditionally only dealt with user and supervisor modes, it only makes use of levels 0 (supervisor) and 3 (user).

To get a glimpse of how this can work, check out http://www.codeguru.com/Cpp/W-P/system/devicedriverdevelopment/article.php/c8035/.  This is for Windows NT, but you should now be able to read such an article to glean some information about how the hardware could be used to effect what is needed in UNIX.